A place to keep my synthesizable verilog examples.
This repository collects all information about TPU architecture, programming, and provides tutorials.
XMM Architecture: An open hardware specification for decentralized, high-bandwidth compute-attached memory.
Structured disclosure and Mach-O dissection of Apple A18 Always-On (AON) processor design.
Sovereign — A Geometric Substrate for Persistent Intelligence A unified cognitive substrate architecture integrating memory, compression, geometry, and identity.
My work on the project-based course NAND2TETRIS.
Enterprise-grade IoT platform for live AC power profiling. Utilizes ESP32 edge processing, MQTT, and a Python analytics engine to monitor True-RMS voltage/current, predict billing costs, and prevent circuit overloads via automated relay actuation and a live Chart.js web dashboard.
Project JANUS: 100-Gbaud One-Hot Spatial Photonic Modular Processor. Delivers 1.64 PetaMAC/s in a 100 mm² monolithic 3D die at 6.17 W TDP (0.264 pJ/MAC) using Fermat-prime RNS ({17, 257}), non-volatile Sb2S3 phase-change routing (0 W hold), and TIA/ADC-free StrongARM receivers. Includes full GDS II tapeout layouts and multi-physics verification.
Enterprise-grade IoT platform for real-time waste bin telemetry. Uses ESP32, HC-SR04 sensors, and MQTT to orchestrate live dashboards, Python simulations, PDF reporting, and automated fleet dispatching. Replaces static waste collection with data-driven routing.
Timestamped GPIO I/O research: physically verified M0; later architectural utility gates failed and development ended.
Implementation AES-128 encryption using a single reusable round datapath, registered state and key storage, on-the-fly key expansion, and a four-state FSM-based controller. All ten AES rounds share one combinational datapath; resource reuse is traded for throughput relative to a fully unrolled or pipelined design.
A design proposal for photonic GPU interconnects that use optical path geometry itself as the synchronization clock — no centralized timing tree required.
Where approximate arithmetic can go in FIP/FFIP matrix-multiply accelerators: placement law validated in RTL and ResNets, plus 28 nm FD-SOI ASIC results (FIP -14.2% area, -18.8% power)
Frozen programmable serial-I/O research: bounded v3 generalization passed; physical campaign stopped without qualification.
Hashira X9 is an autonomous Edge-IoT security node engineered to intercept environmental and physical threats. Running a custom, non-blocking C++ Finite State Machine (v8.1.0) on an ATMega328P, it provides multi-vector hazard isolation (fire, gas, tampering) with zero blind spots.
The AGX Oberon project is documentation for a new type of high level computer architecture using PS5 silicon to build a powerful mini-supercomputer, using AMD and/or Nvidia GPU hardware for LLM, at an considerably lower cost.
A theoretical hardware architecture framework for the post-silicon era based on on radiation-evacuated lithium niobate on sapphire (LNOS)
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